Do crystals datasheets usually not tell the jitter spec? Do we usually measure the jitter ourselves?
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How am I supposed to know 'the source latency'?
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Whose '1000 cycles' is this? What does 'a setup path requirement of 0.01 ns' mean?
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What's a 'die pad' in an FPGA chip?
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What do the backslashes mean?
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Do we need to do some settings to allow uniquification?
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Are setup time slacks in an implemented result always shorter than the corresponding setup time slacks in a synthesis result?
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Can I create folders under a constraint set to organize the constraint files in Vivado?
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What does 'compilation' mean in Vivado?
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What are these codes?
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Why can they use blocking assignment for a register here?
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What should be done with the pins not used in a multiplexer compacted in a slice in 7 series FPGAs?
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What do I do if Google doesn't recognies my new device?
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How can this clock gating technique save power?
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Why is there a '2**' before 'RAM_ADDRBITS'?
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What is PLL (phase lock loop) good for?
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Is the real data type synthesizable in systemverilog?
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Why is there no "x in $monitor is 5"? Can't the inactive region "#0 x = 5;" trigger the "$monitor" in Postponed region?
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Why is F8 pin not in the device picture provided by Vivado?
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What do S and M stand for in this picture?
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What are some IP cores in Xlinx (7 series) that a beginner should familiar themself with?
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Would you ever use a counter to devide the clock frequency to get a new clock?
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What does 'unique' mean here? I'm reading about the synthesis flow.
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What would happen here? They assign value and minus 1 at the same time.
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What does 'power users' mean here? Why is that function not available for non-power users?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
